ST92F124JDV2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F124JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS

I2C/DDC-BUS TIMING TABLE

(VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified)

Symbol

fINTCLK

fSCL

TBUF

THIGH

TLOW

THD:STA

TSU:STA

THD:DAT

TSU:DAT

TR

TF

TSU:STO

Cb

Parameter

Internal Frequency (Slave Mode)

SCL clock frequency

Bus free time between a STOP and

START condition

SCL clock high period

Standard Mode

SCL clock low period

Fast Mode

Hold time START condition. After this

period, the first clock pulse is generated

Set-up time for a repeated START condi-

tion

Data hold time

FREQ[2:0] = 000

FREQ[2:0] = 001

FREQ[2:0] = 010

FREQ[2:0] = 011

Data set-up time

(Without SCL stretching)

Data set-up time

(With SCL stretch-

ing)

FREQ[2:0] = 000

FREQ[2:0] = 001

FREQ[2:0] = 010

FREQ[2:0] = 011

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Capacitive load for each bus line

Formula

TLOW + Tck

TLOW + THIGH

– THD:STA

3 x Tck

4 x Tck

4 x Tck

10 x Tck

TLOW – THD:DAT

7 x Tck

15 x Tck

15 x Tck

31 x Tck

TLOW + THIGH

– THD:STA

Protocol Specifications

Standard I2C

Fast I2C

Min Max

Min

Max

2.5

2.5

0

100

0

400

4.7

1.3

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0 (1;2)

0 (1;2)

0.9 (1;3)

250(1)

100 (1)

4.0(1)

1000 (1)

300 (1)

20+0.1Cb (1)

20+0.1Cb (1)

0.6 (1)

400

400

Unit

MHz

kHz

µs

µs

µs

µs

µs

µs

ns

ns

ns

ns

pF

Note:

(1) Value guaranteed by design.

(2) The ST9 device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the fall-

ing edge of SCL

(3) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal

Legend:

Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;

2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;

Crystal Oscillator Clock period x PLL factor when the PLL is enabled.

Cb = total capacitance of one bus line in pF

FREQ[2:0] = Frequency bits value of I2C Own Address Register 2 (I2COAR2)

I2C TIMING

SDA

t BUF

t LOW

tR

tF

t HD:STA

t SP

SCL

P

t HD:STA

S

t HD:DAT

t HIGH

t SU:DAT

t SU:STA

Sr

t SU:STO

P

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