ST92F124JDV2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F124JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS

J1850 BYTE LEVEL PROTOCOL DECODER TIMING TABLE

(VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified)

Symbol

Parameter

TF

TIB

TP0

TA0

TP1

TA1

TNBS

TNBL

TSOF

TEOD

TEOF

TBRK

TIDLE

Symbols Filtered

Invalid Bit Detected

Passive Data Bit “0”

Active Data Bit “0”

Passive Data Bit “1”

Active Data Bit “1”

Short Normalization Bit

Long Normalization Bit

Start Of Frame Symbol

End Of Data Symbol

End Of Frame Symbol

Break Symbol

Idle Symbol

Value

Receive Mode Transmission Mode Unit

Min

Max

Nominal

0

≤7

-

µs

>7

≤ 34

-

µs

> 34

≤ 96

64

µs

> 96

≤ 163

128

µs

> 96

≤ 163

128

µs

> 34

≤ 96

64

µs

> 34

≤ 96

64

µs

> 96

≤ 163

128

µs

> 163 ≤ 239

200

µs

> 163 ≤ 239

200

µs

> 239

-

280

µs

> 239

-

300

µs

> 280

-

300

µs

Note

(1)(2)

(1)(2)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

(1)(2)(3)

Note:

(1) Values obtained with internal frequency at 24 MHz (INTCLK), with CLKSEL Register set to 23.

(2) In Transmission Mode, symbol durations are compliant to nominal values defined by the J1850 Protocol Specifications.

(3) All values are reported with a precision of ±1 µs.

J1850 PROTOCOL TIMING

T SOF T P0 T A0 T P1 T A1

VPWO

T EOD T NBS

T IDLE

T EOF

T SOF T P0 T A0 T P1 T A1

VPWO

T EOD

T NBL

T IDLE

T EOF

400/429

1

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