LTC2283I View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC2283I

Dual 12-Bit, 125Msps Low Power 3V ADC

Linear Technology 

LTC2283

APPLICATIONS INFORMATION

SINUSOIDAL

CLOCK

INPUT

4.7μF

0.1μF 1k

CLEAN

SUPPLY

FERRITE

BEAD

0.1μF

CLK LTC2283

50Ω 1k NC7SVU04

4.7μF

CLEAN

SUPPLY

FERRITE

BEAD

0.1μF

100Ω

CLK LTC2283

2283 F11

Figure 11. Sinusoidal Single-Ended CLK Drive

The noise performance of the LTC2283 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

In applications where jitter is critical, such as when digi-

tizing high input frequencies, use as large an amplitude

as possible. Also, if the ADC is clocked with a sinusoidal

signal, filter the CLK signal to reduce wideband noise and

distortion products generated by the source.

It is recommended that CLKA and CLKB are shorted to-

gether and driven by the same clock source. If a small time

delay is desired between when the two channels sample

the analog inputs, CLKA and CLKB can be driven by two

different signals. If this delay exceeds 1ns, the performance

of the part may degrade. CLKA and CLKB should not be

driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting a

differential clock to the single-ended CLK input. The use

of a transformer provides no incremental contribution

to phase noise. The LVDS or PECL to CMOS translators

provide little degradation below 70MHz, but at 140MHz will

degrade the SNR compared to the transformer solution.

The nature of the received signals also has a large bear-

ing on how much SNR degradation will be experienced.

For high crest factor signals such as WCDMA or OFDM,

where the nominal power level must be at least 6dB to

8dB below full scale, the use of these translators will have

a lesser impact.

2283 F12

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

DIFFERENTIAL

CLOCK

INPUT

ETC1-1T

CLK LTC2283

5pF-30pF

0.1μF FERRITE

BEAD

2283 F13

VCM

Figure 13. LVDS or PECL CLK Drive Using a Transformer

The transformer in the example may be terminated with

the appropriate termination for the signaling in use. The

use of a transformer with a 1:4 impedance ratio may be

desirable in cases where lower voltage differential signals

are considered. The center tap may be bypassed to ground

through a capacitor close to the ADC if the differential

signals originate on a different plane. The use of a ca-

pacitor at the input may result in peaking, and depending

on transmission line length may require a 10Ω to 20Ω

ohm series resistor to act as both a low pass filter for

high frequency noise that may be induced into the clock

line by neighboring digital signals, as well as a damping

mechanism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2283 is 125Msps.

The lower limit of the LTC2283 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

2283fb

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