LTC2283I View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC2283I Datasheet PDF : 24 Pages
| |||
LTC2283
APPLICATIONS INFORMATION
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2283 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit. Note that
OF is high when an overflow or underflow has occurred
on either Channel A or Channel B.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
D11 – D0
OF (Offset Binary)
>+1.000000V
+0.999512V
+0.999024V
1 1111 1111 1111
0 1111 1111 1111
0 1111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0 1000 0000 0001
0 1000 0000 0000
0 0111 1111 1111
0 0111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0 0000 0000 0001
0 0000 0000 0000
1 0000 0000 0000
D11 – D0
(2’s Complement)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2283 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
VDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
OE
LTC2283
OVDD 0.5V
VDD
TO 3.6V
0.1μF
OVDD
43Ω
TYPICAL
DATA
OUTPUT
OGND
2283 F14
Figure 14. Digital Output Buffer
Data Format
Using the MODE pin, the LTC2283 parallel digital output
can be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3VDD selects offset binary
output format. Connecting MODE to 2/3VDD or VDD selects
2’s complement output format. An external resistor divider
can be used to set the 1/3VDD or 2/3VDD logic values.
Table 2 shows the logic states for the MODE pin.
2283fb
17
Share Link: 