LTM2883 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTM2883

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power

Linear Technology 

LTM2883

Applications Information

parasitic cable inductance along with the high Q char-

acteristics of ceramic capacitors can cause substantial

ringing which could exceed the maximum voltage ratings

and damage the LTM2883. Refer to Linear Technology Ap-

plication Note 88, entitled Ceramic Input Capacitors Can

Cause Overvoltage Transients for a detailed discussion

and mitigation of this phenomenon.

Isolated Supply Adjustable Operation

The three isolated power rails may be adjusted by con-

nection of a single resistor from the adjust pin of each

output to its associated output voltage or to GND2. The

pre-configured voltages represent the maximums for

guaranteed performance. Figure 5 illustrates configura-

tion of the output power rails for VCC2 = 3.3V, V+ = 10V,

and V– = –10V.

LTM2883-5S

5V

VCC

VL

ON

SDOE

CS

SDI

SCK

DO2

SDO

DO1

GND

VCC2

AVCC2

V+

AV+

V–

AV–

174k

530k

530k

3.3V

10V

–10V

CS2

SDI2

SCK2

I2

SDO2

I1

GND2

2883 F05

Figure 5. Adjustable Voltage Rails

To decrease the output voltage a resistor must be connected

from the output voltage pin to the associated adjust pin.

To increase the output voltage connect a resistor to the

adjust pin to GND2. Use the equations listed in Table 1

to calculate the resistances required to adjust each output.

The output voltage adjustment range for VCC2 is 3V to 5.5V.

Adjustment range for V+ and V– is ±1.22V to approximately

±13.5V. Operation at low output voltages for V+ or V– may

result in thermal shutdown due to low dropout regulator

power dissipation.

Table 1. Voltage Adjustment Formula

OUTPUT RESISTOR (Ax TO Vx) TO RESISTOR (Ax TO GND2) TO

VOLTAGE

REDUCE OUTPUT

INCREASE OUTPUT

VCC2

( ) 110k • VCC2 – 0.6

5 – VCC2

66k

VCC2 – 5

V+, V–

( ) 150k • V+,V– – 1.22

12.5 – V+ ,V–

183k

V+ ,V– – 12.5

Channel Timing Uncertainty

Multiple channels are supported across the isolation bound-

ary by encoding and decoding of the inputs and outputs. Up

to three signals in each direction are assembled as a serial

packet and transferred across the isolation barrier. The time

required to transfer all 3 bits is 100ns maximum, and sets

the limit for how often a signal can change on the opposite

side of the barrier. Encoding transmission is independent

for each data direction. The technique used assigns SCK or

SCL on the logic side, and SDO2 or I2 on the isolated side,

the highest priority such that there is no jitter on the associ-

ated output channels, only delay. This preemptive scheme

will produce a certain amount of uncertainty on the other

isolation channels. The resulting pulse width uncertainty on

these low priority channels is typically ±6ns, but may vary

up to ±44ns if the low priority channels are not encoded

within the same high priority serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2883-S provides a SPI compatible isolated inter-

face. The maximum data rate is a function of the inherent

channel propagation delays, channel to channel pulse

width uncertainty, and data direction requirements. Chan-

nel timing is detailed in Figures 5 through 8 and Tables

3 and 4. The SPI protocol supports four unique timing

configurations defined by the clock polarity (CPOL) and

clock phase (CPHA) summarized in Table 2.

Table 2. SPI Mode

CPOL CPHA

0

0

0

1

1

0

1

1

DATA TO (CLOCK) RELATIONSHIP

Sample (Rising)

Set-Up (Falling)

Set-Up (Rising)

Sample (Falling)

Sample (Falling)

Set-Up (Rising)

Set-Up (Falling)

Sample (Rising)

2883f

17

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