LTM2883 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTM2883

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power

Linear Technology 

LTM2883

Applications Information

• SDI to SCK (master data write to slave)

t2 → t4

t5 → t6

t2 → t5

≈50ns, SDI to SDI2 propagation delay

≈50ns, SCK to SCK2 propagation delay

≥50ns, SDI to SCK, separate packet

non-zero set-up time

t4 → t6 ≥50ns, SDI2 to SCK2, separate packet

non-zero set-up time

• SDO to SCK (master sample SDO, subsequent

SDO valid)

t8

set-up data transition SDI and SCK

t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2

propagation delay

t10

SDO2 data transition in response to SCK2

t10 → t11 ≈50ns, SDO2 to SDO propagation delay

t11 → t12 Set-up time for master SDO to SCK

Table 3. Bidirectional SPI Timing Event Description

TIME

CPHA EVENT DESCRIPTION

t0

0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output

enabled, initial data is not equivalent to slave device data output

t0 to t1, t17 to t18

t1

t2

0, 1 Propagation delay chip select, logic to isolated side, 50ns typical

0, 1 Slave device chip select output data enable

0

Start of data transmission, data set-up

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t1 to t3

t3

t2 to t4

0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical

0, 1 Slave data output valid, logic side

0

Propagation delay of data, logic side to isolated side

1

Propagation delay of data and clock, logic side to isolated side

t5

t5 to t6

t6

t8

t7 to t8

t8 to t9

t8 to t10

t10, t14

t10 to t11, t14 to t15

t11 to t12

t13

0, 1 Logic side data sample time, half clock period delay from data set-up transition

0, 1 Propagation delay of clock, logic to isolated side

0, 1 Isolated side data sample time

0, 1 Synchronous data and clock transition, logic side

0, 1 Data to clock delay, must be ≤13ns

0, 1 Clock to data delay, must be ≤3ns

0, 1 Propagation delay clock and data, logic to isolated side

0, 1 Slave device data transition

0, 1 Propagation delay slave data, isolated to logic side

0, 1 Slave data output to sample clock set-up time

0

Last data and clock transition logic side

1

Last sample clock transition logic side

t13 to t14

0

Propagation delay data and clock, logic to isolated side

1

Propagation delay clock, logic to isolated side

t15

0

Last slave data output transition logic side

1

Last slave data output and data transition, logic side

t15 to t16

t17

t18

1

Propagation delay data, logic to isolated side

0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side

0, 1 Chip select transition isolated side, slave data output disabled

2883f

19

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