M41T83SQA6E View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41T83SQA6E

Serial RTC with battery switchover

STMicroelectronics 

Clock operation

M41T82 M41T83

3.6

Optional second programmable alarm

When the Alarm 2 Enable (AL2E) bit (D1 of address 13h) is set to a logic ‘1’, registers 14h

through 18h provide control for a second programmable alarm which operates in the same

manner as the alarm function described above. The A2IE (Alarm 2 Interrupt Enable) bit

allows the second alarm to trigger a separate interrupt output (IRQ2).

The AL2E bit defaults on initial power-up to a logic ‘0’ (Alarm 2 disabled). In this mode, the

five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of

user SRAM.

The IRQ1/FT/OUT pin can also be activated in the battery back-up mode (see Figure 22 on

page 36).

Figure 21. Alarm interrupt reset waveform

0Eh

0Fh

00h

ALARM FLAG BITS (AFx)

IRQ1/FT/OUT or

IRQ2

HIGH-Z

AI08898

Figure 22. Back-up mode alarm waveform

VCC

VPFD

VSO

AF Bit in Flags

Register

IRQ1/FT/OUT or

IRQ2

HIGH-Z

1. ABE and A1IE bits = 1.

trec

AI09164c

36/58

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