M41T83SQA6E View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41T83SQA6E

Serial RTC with battery switchover

STMicroelectronics 

Clock operation

M41T82 M41T83

3.8

3.8.1

Note:

8-bit (countdown) timer

The Timer Value Register is an 8-bit binary countdown timer. It is enabled and disabled via

the Timer Control Register (11h) TE bit. Other timer properties such as the source clock, or

interrupt generation are also selected in the Timer Control Register (see Table 9). For

accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a

frequency of at least twice the selected timer clock.

The Timer Control register selects one of four source clock frequencies for the timer (4096,

64, 1, or 1/60Hz), and enables/disables the timer. The timer counts down from a software-

loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF)

bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also

be used to generate an interrupt (IRQ1/FT/OUT) on the M41T83. The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal

which follows the condition of TF. The Timer Interrupt/Timer Pulse (TI/TP) bit is used to

control this mode selection. When reading the timer, the current countdown value is

returned.

Table 9. Timer control register map(1)

Addr D7

D6

D5

D4

D3

D2

D1

D0

0Fh WDF AF1 AF2 BL

TF

OF

0

0

10h

Timer countdown value

11h TE TI/TP TIE

0

0

0

1. Bit positions labeled with ‘0’ should always be written with logic '0.'

TD1

TD0

Function

Flags

Timer value

Timer control

Timer Interrupt/Timer Pulse (TI/TP, M41T83 only)

● TI/TP = 0

IRQ1/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt

Enable bit (TIE).

● TI/TP = 1

IRQ1/FT/OUT pulses are active when TF is logic '1' according to Table 10 (subject to

the status of the TIE bit).

If an Alarm condition, Watchdog time-out, Oscillator Failure, or OUT = 0 causes

IRQ1/FT/OUT to be asserted low, then IRQ1/FT/OUT will remain asserted even if TI/TP is

set to '1'. When in pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on

IRQ1/FT/OUT. The output pulses will only stop if TE, TIE, or TI/TP are reset to '0'.

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