M45PE40-VMP6TP View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M45PE40-VMP6TP
STMicroelectronics
M45PE40-VMP6TP Datasheet PDF : 35 Pages
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M45PE40
Table 12. AC Characteristics (25MHz operation)
Test conditions specified in Table 8. and Table 9.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following
fC
fC
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
D.C.
RDSR
25
MHz
fR
Clock Frequency for READ
instructions
D.C.
20
MHz
tCH 1
tCLH
Clock High Time
18
ns
tCL 1
tCLL
Clock Low Time
18
ns
Clock Slew Rate 2 (peak to peak)
0.03
V/ns
tSLCH
tCSS
S Active Setup Time (relative to C)
10
ns
tCHSL
S Not Active Hold Time (relative to C)
10
ns
tDVCH
tDSU
Data In Setup Time
5
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
10
ns
tSHCH
S Not Active Setup Time (relative to C)
10
ns
tSHSL
tCSH
S Deselect Time
200
ns
tSHQZ 2
tDIS
Output Disable Time
15
ns
tCLQV
tV
Clock Low to Output Valid
tCLQX
tHO
Output Hold Time
0
15
ns
ns
tRLRH 2
tRST
Reset Pulse Width
10
µs
tRHSL
tREC
Reset Recovery Time
3
µs
tSHRH
Chip should have been deselected
before Reset is de-asserted
10
ns
tWHSL
Write Protect Setup Time
50
ns
tSHWL
Write Protect Hold Time
100
ns
tDP 2
S to Deep Power-down
3
µs
tRDP 2
S High to Standby Power mode
30
µs
tPW (3)
Page Write Cycle Time (256 Bytes)
Page Write Cycle Time (n Bytes)
11
10.2+
25
ms
n*0.8/256
tPP (3)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.2
0.4+
5
ms
n*0.8/256
tPE
Page Erase Cycle Time
10
20
ms
tSE
Sector Erase Cycle Time
1
5
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
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