M48Z2M1V-85PL1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48Z2M1V-85PL1 Datasheet PDF : 20 Pages
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Operation modes
M48Z2M1Y, M48Z2M1V
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z2M1Y
–70
M48Z2M1V
–85
Unit
Min Max Min Max
tAVAV
WRITE cycle time
70
85
ns
tAVEH Address valid to chip enable high
65
75
ns
tAVEL Address valid to chip enable low
0
0
ns
tAVWH Address valid to WRITE enable high
65
75
ns
tAVWL Address valid to WRITE enable low
0
0
ns
Obsolete Product(s) - Obsolete Product(s) 2.3
tDVEH
tDVWH
tEHAX
tEHDX
tELEH
tWHAX
tWHDX
tWHQX(2)(3)
tWLQZ(2)(3)
tWLWH
Input valid to chip enable high
Input valid to WRITE enable high
Chip enable high to address transition
Chip enable high to input transition
Chip enable low to chip enable high
WRITE enable high to address transition
WRITE enable high to input transition
WRITE enable high to output transition
WRITE enable low to output Hi-Z
WRITE enable pulse width
30
35
ns
30
35
ns
15
15
ns
10
15
ns
55
75
ns
5
5
ns
0
0
ns
5
5
ns
25
30 ns
55
65
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where
noted).
2. CL = 5 pF (see Figure 9 on page 13).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDEâ„¢ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all
inputs are treated as “Don't care.â€
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, write protection takes
place. When VCC drops below VSO, the control circuit switches power to the internal energy
source which preserves data.
The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the batteries are disconnected, and the power
supply is switched to external VCC. Write protection continues for tER after VCC reaches
VPFD to allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 5135 Rev 6
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