M48Z2M1Y
M48Z2M1V
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
â– Integrated, ultra low power SRAM, power-fail
control circuit, and batteries
â– Conventional SRAM operation; unlimited
) WRITE cycles
t(s â– 10 years of data retention in the absence of
c power
du â– Automatic power-fail chip deselect and WRITE
ro protection
P â– WRITE protect voltages
te (VPFD = power-fail deselect voltage):
le – M48Z2M1Y: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
so – M48Z2M1V: VCC = 3.0 to 3.6 V;
b 2.8 V ≤ VPFD ≤ 3.0 V
O â– Batteries are internally isolated until power is
- applied
t(s) â– Pin and function compatible with JEDEC
standard 2 Mb x 8 SRAMs
uc â– RoHS compliant
Obsolete Prod – Lead-free second level interconnect
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PLDIP36 module
June 2011
Doc ID 5135 Rev 6
This is information on a product still in production but not recommended for new designs.
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