M48Z2M1V-85PL1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48Z2M1V-85PL1 Datasheet PDF : 20 Pages
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M48Z2M1Y, M48Z2M1V
Operation modes
2.2
WRITE mode
The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
Obsolete Product(s) - Obsolete Product(s) Note:
Figure 6. WRITE enable controlled, WRITE mode AC waveforms
A0-A20
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
Output enable (G) = high.
Figure 7. Chip enable controlled, WRITE mode AC waveforms
A0-A20
E
W
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
AI02053
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02054
Note:
Output enable (G) = high.
Doc ID 5135 Rev 6
9/20
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