M50FLW040AN5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Bus operations

Table 7. FWH bus write field definitions

Clock Clock

Cycle Cycle

Number Count

Field

FWH0- Memory

FWH3 I/O

Description

1

1 START 1110b

I

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value

2

1 IDSEL XXXX

I

on FWH0-FWH3 is compared to the IDSEL strapping on

the FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

A 28-bit address is transferred, with the most significant

nibble first. Address lines A19-21 and A23-27 are treated

3-9

7 ADDR XXXX I as Don’t Care during a normal memory array access, with

A22=1, but are taken into account for a register access,

with A22=0. (See Table 15)

10

1 MSIZE XXXX

I

0000(Single Byte Transfer) 0001 (Double Byte Transfer)

0010b (Quadruple Byte Transfer).

11-18 M=2/4/8 DATA XXXX

previous

+1

1

TAR 1111b

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with

A1-

I A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11. In Double Byte Program the first pair of nibbles is that

at the address with A0 set to 0, the second pair with A0 set

to 1)

I

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

previous

+1

1

TAR

1111b

(float)

O

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

previous

+1

1

SYNC 0000b

O

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

previous

+1

1

TAR 1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

previous

+1

1

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs and the host

takes control of FWH0-FWH3.

Figure 7. FWH bus write waveforms

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

1

IDSEL

1

ADDR

7

MSIZE

1

DATA

M

TAR

2

SYNC

1

TAR

2

AI08434B

23/64

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