M50FLW040AN5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

Bus operations

M50FLW040A, M50FLW040B

Table 8. LPC bus read field definitions (1-byte)

Clock

Cycle

Number

Clock

Cycle

Count

Field

LAD0- Memory

LAD3 I/O

Description

On the rising edge of CLK with LFRAME Low,

1

1

START 0000b

I

the contents of LAD0-LAD3 must be 0000b to

indicate the start of a LPC cycle.

Indicates the type of cycle and selects 1-byte

2

1

CYCTYPE

+ DIR

0100b

I

reading. Bits 3:2 must be 01b. Bit 1 indicates

the direction of transfer: 0b for read. Bit 0 is

Don’t Care.

3-10

A 32-bit address is transferred, with the most

significant nibble first. A23-A31 must be set to

8

ADDR XXXX

I 1. A22=1 for memory access, and A22=0 for

register access. Table 5 shows the appropriate

values for A21-A19.

11

1

TAR 1111b

I

The host drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

12

13-14

15

1

TAR

1111b

(float)

O

The LPC Flash Memory takes control of

LAD0-LAD3 during this cycle.

The LPC Flash Memory drives LAD0-LAD3 to

2

WSYNC 0101b

O

0101b (short wait-sync) for two clock cycles,

indicating that the data is not yet available.

Two wait-states are always included.

The LPC Flash Memory drives LAD0-LAD3 to

1

RSYNC 0000b O 0000b, indicating that data will be available

during the next clock cycle.

16-17

2

18

1

DATA XXXX

O

Data transfer is two CLK cycles, starting with

the least significant nibble.

TAR

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to

1111b to indicate a turnaround cycle.

19

1

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs, the

host takes control of LAD0-LAD3.

Figure 8. LPC bus read waveforms (1-byte)

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

1

CYCTYPE

+ DIR

1

ADDR

8

TAR

2

SYNC

3

DATA

2

TAR

2

AI04429

24/64

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