M58BW016BT100T3(2003) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M58BW016BT100T3
(Rev.:2003)
(Rev.:2003)
STMicroelectronics
M58BW016BT100T3 Datasheet PDF : 63 Pages
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Table 20. Synchronous Burst Read AC Characteristics
Symbol
Parameter
Test Condition
tAVLL Address Valid to Latch Enable Low
E = VIL
tBHKH
Burst Address Advance High to Valid Clock
Edge
E = VIL, G = VIL,
L = VIH
tBLKH
Burst Address Advance Low to Valid Clock
Edge
E = VIL, G = VIL,
L = VIH
tELLL Chip Enable Low to Latch Enable low
tGLQV Output Enable Low to Output Valid
E = VIL, L = VIH
tKHAX Valid Clock Edge to Address Transition
E = VIL
tKHLL Valid Clock Edge to Latch Enable Low
E = VIL
tKHLX Valid Clock Edge to Latch Enable Transition
E = VIL
tKHQX Valid Clock Edge to Output Transition
E = VIL, G = VIL,
L = VIH
tLLKH Latch Enable Low to Valid Clock Edge
E = VIL
tQVKH(1) Output Valid to Valid Clock Edge
E = VIL, G = VIL,
L = VIH
tRLKH Valid Data Ready Low to Valid Clock Edge
E = VIL, G = VIL,
L = VIH
tKHQV Valid Clock Edge to Output Valid
E = VIL, G = VIL,
L = VIH
Note: 1. Data output should be read on the valid clock edge.
2. For other timings see Table 16, Asynchronous Bus Read Characteristics.
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
M58BW016
Unit
80 90 100
0
0
0
ns
8
8
8
ns
8
8
8
ns
0
0
0
ns
25 25 25 ns
5
5
5
ns
0
0
0
ns
0
0
0
ns
3
3
3
ns
6
6
6
ns
6
6
6
ns
6
6
6
ns
11 11 11 ns
Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
K
tKHQV
DQ0-DQ31
n
n+1
n+2
n+3
n+4
n+5
tQVKH
Q0
Q1
Q2
Q3
Q4
Q5
tKHQX
SETUP
Burst Read
Q0 to Q3
Note: n depends on Burst X-Latency
Note: For set up signals and timings see Synchronous Burst Read.
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AI04408b
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