M69KB096AB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M69KB096AB

64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM

STMicroelectronics 

M69KB096AB

5 Standard Asynchronous operating modes

5 Standard Asynchronous operating modes

The M69KB096AB supports Asynchronous Read and Write modes (Random Read, Page

Read, Asynchronous Write).

The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to ‘1’. The Page

mode is controlled by the Refresh Configuration Register (bit RCR7).

During asynchronous operations, the WAIT signal should be ignored and the Clock input signal

K should be held Low, VIL.

Refer to Table 3: Standard Asynchronous Operating Modes for a detailed description of

asynchronous operating modes.

5.1 Asynchronous Read and Write modes

At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to ‘1’).

This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are

initiated by bringing E and G Low, VIL, while keeping W High, VIH. Valid data will be gated

through the output buffers after the specific access time tELQV has elapsed.

Write operations occur when E and W are Low. During Asynchronous Random Write

operations, the G signal is ‘don't care’ and W will override G. The data to be written is latched

on the rising edge of E, W, LB or UB (whichever occurs first). The write operation is terminated

by de-asserting E, W, LB or UB.

The L input can either be used to latch the address or kept Low, VIL, during the entire read/write

operation.

See Figures 14 and 15, and Table 17 for details on Asynchronous Read AC waveforms and

characteristics and Figures 18, 19, 20, and Table 19 for details of Asynchronous Write AC

waveforms and characteristics.

5.2 Asynchronous Page Read mode

Asynchronous Page Read mode is enabled by setting RCR7 to ‘1’. The Latch Enable, L, and

the Chip enable E must be held Low, VIL during Asynchronous Page Read operations.

A Page of data is internally read. A memory page may consist of 4, 8 or 16 Words. During a 4-

Word page access, all the address bits except A0 to A1 should be fixed. During a 8-Word and

16-Word page access, all address bits are fixed except A0 to A2 and A0 to A3, respectively

(see Table 2: Page Mode Characteristics).

The first read operation within the Page has the normal access time (tAVQV), subsequent reads

within the same Page have much shorter access times (tAVQV1). If the Page changes then the

normal, longer timings apply again.

The Page mode is not available for write operations.

See Figure 16 and Table 17 for details of the Asynchronous Page Read timing requirements.

15/73

Share Link: