M69KB096AB
5 Standard Asynchronous operating modes
Table 3. Standard Asynchronous Operating Modes
Asynchronous
Modes(1)(2)
Power
E
W
G
UB
LB
CR A19 A18
A0-A17
A20-A21
DQ0-DQ7 DQ8-DQ15
Word Read
Lower Byte
Read
VIL VIL VIL VIL
VIH VIL VIH VIL VIL
Valid
Valid
Output
Valid
Output
Valid
Output
Valid
High-Z
Upper Byte
Read
VIL VIL VIH VIL
Valid
High-Z
Output
Valid
Word Write
Lower Byte
Write
Upper Byte
Write
Read
Configuration
Register
(CR Controlled
Method)
Program
Configuration
Register (CR
Controlled)(3)
X VIL VIL VIL
Active
(ICC)
VIL
VIL
X VIH VIL VIL
X VIL VIH VIL
Valid
Valid
Valid
Input Valid Input Valid
Input Valid Invalid
Invalid Input Valid
VIH VIL X
VIL X X
00(RCR)
X
10(BCR)
X
X1(DIDR)
VIH
00(RCR)
BCR/
X
10(BCR)
(4)
RCR Data
BCR/
RCR/DIDR
Content
X
Output Disable/
No Operation
Active
(ICC)
VIH VIH X X VIL X X
X
Deep
Deep
Power-
Power-Down(5)
Down VIH X X X
X
X
X
X
X
(ICCPD)
Standby
Standby
(IPASR)
VIH X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
1. The Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and
Deep Power-Down modes.
2. The device must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
3. BCR and RCR only.
4. A18 and A19 are used to select the BCR, RCR or DIDR registers.
5. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep Power-
Down mode.
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