MB90P663APFM View Datasheet(PDF) - Fujitsu
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MB90P663APFM Datasheet PDF : 84 Pages
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MB90660A Series
Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW A
POPW AH
POPW PS
POPW rlst
JCTX @A
AND
OR
CCR, #imm8
CCR, #imm8
MOV RP, #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
MOV
MOV
A, brgl
brg2, A
NOP
ADB
DTB
PCB
SPB
NCC
CMR
# ~ RG B
Operation
14
0 (c) word (SP) ← (SP) –2, ((SP)) ← (A)
14
0 (c) word (SP) ← (SP) –2, ((SP)) ← (AH)
14
0 (c) word (SP) ← (SP) –2, ((SP)) ← (PS)
2 *3 *5 *4 (SP) ← (SP) –2n, ((SP)) ← (rlst)
13
0 (c) word (A) ← ((SP)), (SP) ← (SP) +2
13
0 (c) word (AH) ← ((SP)), (SP) ← (SP) +2
14
0 (c) word (PS) ← ((SP)), (SP) ← (SP) +2
2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) +2n
1 14 0 6× (c) Context switch instruction
23
0
0 byte (CCR) ← (CCR) and imm8
23
0
0 byte (CCR) ← (CCR) or imm8
22
0
0 byte (RP) ←imm8
22
0
0 byte (ILM) ←imm8
23
1
2+ 2+ (a) 1
21
0
2+ 1+ (a) 0
0 word (RWi) ←ear
0 word (RWi) ←eam
0 word(A) ←ear
0 word (A) ←eam
23
0
0 word (SP) ← (SP) +ext (imm8)
33
0
0 word (SP) ← (SP) +imm16
2
*1
0
0 byte (A) ← (brgl)
21
0
0 byte (brg2) ← (A)
11
0
0 No operation
11
0
0 Prefix code for accessing AD space
11
0
0 Prefix code for accessing DT space
11
0
0 Prefix code for accessing PC space
11
0
0 Prefix code for accessing SP space
11
0
0 Prefix code for no flag change
11
0
0 Prefix code for common register bank
LH AH I S T N Z V C RMW
––––––––– –
––––––––– –
––––––––– –
––––––––– –
–*––––––– –
––––––––– –
–– * * * * * * * –
––––––––– –
–– * * * * * * * –
–– * * * * * * * –
–– * * * * * * * –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
–*––––––– –
–*––––––– –
––––––––– –
––––––––– –
Z*––– * *–– –
––––– * *–– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
77
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