MCF51QM32VFM(2012) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MCF51QM32VFM
(Rev.:2012)

Embedded - Microcontrollers, Integrated Circuits (ICs)

Freescale Semiconductor 

Communication interfaces

6.8 Communication interfaces

6.8.1 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables

provide timing characteristics for classic SPI timing modes. See the SPI chapter of the

chip's Reference Manual for information about the modified transfer formats used for

communicating with slower peripheral devices.

All timing is shown with respect to 20% VDD and 70% VDD, unless noted, as well as

input signal transitions of 3 ns and a 50 pF maximum load on all SPI pins. All timing

assumes slew rate control is disabled and high drive strength is enabled for SPI output

pins.

Table 32. SPI master mode timing

Num.

1

Symbol Description

fop

Frequency of operation

2

tSPSCK SPSCK period

3

tLead Enable lead time

4

tLag

Enable lag time

5

tWSPSCK Clock (SPSCK) high or low time

6

tSU

Data setup time (inputs)

7

tHI

Data hold time (inputs)

8

tv

Data valid (after SPSCK edge)

9

tHO

Data hold time (outputs)

10

tRI

Rise time input

tFI

Fall time input

11

tRO

Rise time output

tFO

Fall time output

Min.

fBUS/2048

Max.

fBUS/2

2 x tBUS

1/2

1/2

tBUS - 30

21

0

—

0

—

2048 x

tBUS

—

—

1024 x

tBUS

—

—

25

—

tBUS - 25

Unit

Hz

ns

tSPSCK

tSPSCK

ns

Comment

fBUS is the

bus clock

as defined

in Table 8.

tBUS = 1/

fBUS

—

—

—

ns

—

ns

—

ns

—

ns

—

ns

—

—

25

ns

—

MCF51QM128 Data Sheet, Rev. 6, 01/2012.

Freescale Semiconductor, Inc.

49

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