MH8S72PHC-10 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
Manufacturer
MH8S72PHC-10 Datasheet PDF : 55 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72PHC -7,-8,-10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to
the /CAS Latency.As a result, READ to PRE interval determines valid data length to be
output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CL=3
CK
Command
DQ
Command
DQ
Command
DQ
READ
PRE
READ
Q0 Q1 Q2
PRE
READ PRE
Q0 Q1
Q0
CL=2
Command
DQ
Command
DQ
Command
DQ
READ
PRE
Q0 Q1 Q2
READ
PRE
Q0 Q1
READ PRE
Q0
MIT-DS-0283-0.0
MITSUBISHI
ELECTRIC
( 23 / 55 )
9/ Dec. /1998
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