MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

Pin Description (continued)

PBGA

Ball Number

U20

W17, Y17, V16,

W16, Y16, V15,

W15, Y15

V17

Y20

Y19

W14

Y14

W18

Y18

V20

V19

W8

Y8

V1

W1

Y1

Name

Description

CTREF2

LREF0- 7

CT-Bus Reference 2 (5 V Tolerant Input). This pin accepts 8KHz,

1.544 MHz or 2.048 MHz network timing reference.

Local Reference (5 V Tolerant Inputs). These pins accept 8 KHz,

1.544 MHz or 2.048 MHz local timing reference.

NREFo

PRI_LOS

SEC_LOS

FAIL_PRI

FAIL_SEC

C32/64o

C1M5o

ST_FPo0

ST_CKo0

ST_FPo1

ST_CKo1

CS

DS

R/W

Network Reference Output (Output). Any local reference can be switched

to this output. The output data rate can be either the same as the selected

reference input data rate or divided to be 8 KHz.

Primary Reference Lost (5 V Tolerant Input). When this signal is high, it

indicates that PRIMARY REFERENCE is not valid. Combined with

SEC_LOS input, this input pin is used in the External Reference Switching

Mode of the DPLL.

Secondary Reference Lost (5 V Tolerant Input). When this signal is high,

it indicates that SECONDARY REFERENCE is not valid. Combined with the

PRI_LOS input, this input pin is used in the External Reference Switching

Mode of the DPLL.

Primary Reference Failure (5 V Tolerant Output). This pin reflects the

logic status of the PLS bit of the DPLL House Keeping Register (DHKR).

When the primary reference fails, this signal goes to 1.

Secondary Reference Failure (5 V Tolerant Output). This pin reflects the

logic status of the SLS bit of the DPLL House Keeping Register (DHKR).

When the secondary reference fails, this signal goes to 1.

C32/64o Clock (5 V Tolerant Output). A 32.768 MHz output clock when the

DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the

DPLL Clock Monitor register bit (CKM) is high.

C1.5o Clock (5 V Tolerant Output). A 1.544 MHz output clock.

ST-Bus Frame Pulse Output (5 V Tolerant Output). The width of this

output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is

8 KHz.

ST-Bus Clock Output (5 V Tolerant Output). The frequency of this output

ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.

ST-Bus Frame Pulse Output (5 V Tolerant Output). The width of this

output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is

8 KHz.

ST-Bus Clock Output (5 V Tolerant Output). The frequency of this output

ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.

Chip Select (5 V Tolerant Input). This active low input is used by the

microprocessor to access the microport.

Data Strobe (5 V Tolerant Input). This active low input works in conjunction

with CS to initiate the read and write cycles.

Read/Write (5 V Tolerant Input). This input controls the direction of the data

bus lines (D0 - D15) during the microprocessor access.

14

Zarlink Semiconductor Inc.

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