MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
Description
W4, Y3, V4, W3,
Y2, V3, W2, V2,
U3, U2, U1, T3,
T2, T1
P3, P2, P1, N2,
N3, N1, M1, M2,
M3, L1, L2, L3,
K1, K2, K3, J3
J1
B9
W13
V11
Y10
W10
W11
Y11
W5
W6
Y4
V6
Y5
Y6
A0 - A13 Address 0 - 13 (5 V Tolerant Inputs). These are the address lines to the
internal memories and registers.
D0 - D15 Data Bus 0 - 15 (5 V Tolerant I/Os). These pins form the 16-bit data bus of
the microport.
DTA
PCI_OE
C64BYPS
TM1
TM2
SG1
AT1
DT1
TMS
TDi
TDo
TCK
TRST
IC0
Data Transfer Acknowledge (5 V Tolerant Output). This active low output
indicates that a data bus transfer is completed. A pull-up resistor is required
to hold a high level.
PCI Output Enable (3.3 V Tolerant Input). This active low input is the
control signal used to tristate the STio0 - 31 pins during hot-swapping.
During normal operation this signal should be low.
PLL Bypass Clock Input (5 V Tolerant Input). Used for device testing. In
functional mode, this input MUST be low.
APLL Test Pin 1 (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
APLL Test Pin 2 (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
APLL Test Control (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
Analog Test Access (5 V Tolerant I/O). Use for APLL testing only. No
connection for normal operation.
Digital Test Access Output (5 V Tolerant Output). Use for APLL testing
only. No connection for normal operation.
Test Mode Select (3.3 V Input with Internal pull-up). JTAG signal that
controls the state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
Test Serial Data In (3.3 V Input with Internal pull-up). JTAG serial test
instructions and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (3.3 V Tolerant Tri-state Output). JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic.
This pin should be low when JTAG is not enabled.
Test Reset (3.3 V Input with Internal pull-up). Asynchronously initializes
the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin
should be pulled low to ensure that the MT90866 is in normal functional
mode.
Leave unconnected for normal operation.
15
Zarlink Semiconductor Inc.
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