MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
LG32
DMS Register Bits
LG31
LG30
Modes
Usable Streams
0
0
0
8.192 Mb/s
0
0
1
4.096 Mb/s
STi12-15, STo12-15
0
1
0
2.048 Mb/s
0
1
1
4-bit subrate
1
0
0
2-bit subrate
Table 5 - Mode Selection for Local STi12 - 15 and ST012 - 15 Streams, Group 3
DMS Register Bits
LG41
LG40
Modes
Usable Streams
0
0
8.192 Mb/s
STi16 - 18, STo16 - 18
0
1
4.096 Mb/s
1
0
2.048 Mb/s
STi16 - 27, STo16 - 27
Table 6 - Mode Selection for Local STi16 - 27 and STo16 - 27 Streams, Group 4
5.0 Local Input Delay Selection
The local input delay selection allows individual local input streams to be aligned and shifted against the input frame
pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface.
Such delays can occur in large centralized and distributed switching system.
Each local input stream can have its own bit delay offset value by programming the local input bit delay selection
registers (LIDR0 to LIDR9). See Table 12, "Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits" on page 50, for
the contents of these registers. Possible bit adjustment can range up to +7 3/4 bit periods forward with resolution of
1/4 bit period. See Table 13 on page 50 and Figure 19 on page 51 for local input delay programming.
6.0 Output Advancement Selection
The MT90866 allows users to advance individual backplane or local output streams with respect to the frame
boundary. This feature is useful in compensating variable output delays caused by various output loading
conditions. Each output stream can have its own advancement value programmed by the output advancement
registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane
output advancement. The local output advancement registers (LOAR0 to LOAR3) are used to program the local
output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution
of 7.5 ns. The advancement is independent of the output data rate. Table 14 on page 52 and Figure 20, "Example
of Backplane Output Advancement Timing" on page 52, and Table 15 on page 53 and Figure 21, "Local Output
Advancement Timing" on page 53 describe the details of the output advancement programming for the backplane
and local interfaces respectively.
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Zarlink Semiconductor Inc.
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