MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

16.0 DPLL

The Digital Phase Locked Loop (DPLL) accepts selectable 1.544 MHz, 2.048 MHz, or 8 kHz input reference

signals. It accepts reference inputs from independent sources and provides bit-error-free reference switching. The

DPLL meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard.

The DPLL also provides the timing for the rest of the MT90866 Digital Switch, generating several network clocks

with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the

requirements of the H.110 clock specification.

The master clock (CLK80M) for the DPLL is provided by the Analog Phase Locked Loop (APLL) from the MT90866

master clock input pin C20i. Since the APLL output is “locked” to the input, the accuracy of CLK80M clock is equal

to the accuracy of C20i.

16.1 MT90866 Modes of Operation

The DPLL, and consequently the MT90866, can, as required by the H.110 standard, operate in three different

modes: Primary Master, Secondary Master and Slave. See Figure 12, "Typical Timing Control Configuration" on

page 32.

To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 20 on page 55 and

Table 21, "DPLL Operation Mode (DOM2) Register Bits" on page 58 for the contents of these registers.

In all modes the MT90866 monitors both the “A Clocks” (C8_A_io and FRAME_A_io) and the “B Clocks” (C8_B_io

and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the “A Clocks” and “B Clocks”

respectively.

CT_C8_A/CT_FRAME_A

CT_C8_B/CT_FRAME_B

CT_NETREF1

CT_NETREF2

LREF0-7

PRIMARY

MASTER

Network Ref

(8kHz / T1 / E1)

LREF0-7

SECONDARY

MASTER

Network Ref

(8kHz / T1 / E1)

LREF0-7

SLAVE

Network Ref

(8kHz / T1 / E1)

LREF0-7

SLAVE

Network Ref

(8kHz / T1 / E1)

Figure 12 - Typical Timing Control Configuration

16.1.1 Primary Master Mode

In the Primary Master Mode, the MT90866 drives the “A Clocks” (C8_A_io and FRAME_A_io), by locking to the

primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference

sources (LREF0-7), or the CTREF1 input or the CTREF2 input. In this mode the MT90866 has the ability to monitor

the primary reference. If the primary reference becomes unreliable, the device continues driving “A Clocks” in

stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference

(SEC_REF) for its network timing. The secondary reference can be provided by one of the local network references

(LREF0-7), the CTREF1 or the CTREF2.

32

Zarlink Semiconductor Inc.

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