MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
These reference signal verifications include a complete loss or a large frequency shift of the selected reference
signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals will return to logic low.
17.6 State Machine Circuit
The State Machine handles the reference selection. Depending on REF_SEL and LOS signals (selection between
FAIL_PRI and PRI_LOS and between FAIL_SEC and SEC_LOS), the state machine selects PRI_REF or
SEC_REF as the current input reference and dictates the PLL Circuit mode: Normal or Holdover Mode. In the
Normal Mode, the DPLL output clocks are locked to the selected input reference (PRI_REF or SEC_REF). In the
Holdover Mode, the DPLL clocks retain the phase and frequency values they had 32 to 64 ms prior to moving from
the Normal to the Holdover Mode. When going from the Holdover to the Normal Mode, the State Machine activates
the MTIE circuit and goes through the states MTIE PRI or MTIE SEC to prevent a phase shift of the output clocks
during the DPLL reference switch (from PRI_REF to SEC_REF and vice versa). The state diagram is given in
Figure 14, "State Machine Diagram" on page 36.
RESET Pin = 0
and xx0
Normal
0
PRI
Normal
4
SEC
RESET Pin = 0
and xx1
0X0 or 011
100 or X01
1XX or X01
MTIE
3
PRI
1X0 or X01
0x0 or
011
0x0 or
X11
MTIE
7
SEC
100 or
X01
Holdover
2
PRI
100 or x01
0x0 or 011
XXX = {LOS_PRI, LOS_SEC, REF_SEL}
0X0 or X1X
Holdover
6
SEC
Figure 14 - State Machine Diagram
18.0 Phase Locked Loop (PLL) Circuit
As shown in Figure 15, "Block Diagram of the PLL Module" on page 37, the PLL module consists of a Skew Control,
Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter,
Digitally Controlled Oscillator (DCO), Divider and Frequency Select MUX modules.
36
Zarlink Semiconductor Inc.
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