MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

17.0 DPLL Functional Description

Data Sheet

REF_SEL

(RPS bit in DOM1)

PRI_LOS Pin

AUTODETECT

(Selected by FDM0-1 bits in DOM2)

SEC_LOS Pin

HOLDOVER_RESET

(HRST bit in DOM2)

PHASE_OFFSET

(POS0-6 bits in DPOA)

MTIE_RESET

(MRST bit in DOM2)

SKEW_CONTROL

(SK0-2 bits in DPOA)

LOS_PRI

State

Machine

(Fig 16)

LOS_SEC

HOLDOVER

MTIE_START

MTIE_DONE

PLL

(Fig 17)

C64

CT_C8

(C8_A_o)

or

(C8_B_o)

C1M5o

FREQ_MOD_PRI

(FP1-0 bits in DOM1)

FREQ_MOD_SEC

(FS1-0 bits in DOM1)

Frequency

Mode

MUX

REF_SELECT

FREQ_MOD

CT_FRAME

(FRAME_A_o)

or

(FRAME_B_o)

PRI_REF

(Selected by SP3-0 bits

in DOM1)

SEC_REF

(Selected by SS3-0 bits

in DOM1)

Reference

Select

MUX

REF

FAIL_PRI

FRAME

CLK80M

C20i APLL

Reference

Monitor

Reference FAIL_SEC

Monitor

FRAME_A_i

FRAME_B_i

Frame

Select

MUX

C8_A_i

C8_B_i

CT Clock

and Frame

Monitor

FAIL_A

CT Clock

and Frame

Monitor

FAIL_B

Figure 13 - DPLL Functional Block Diagram

17.1 Reference Select and Frequency Mode MUX Circuits

The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary

reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference

signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or

FREQ_MOD_SEC) is selected to be the input of the PLL Circuit. The selection is done by the State Machine Circuit

based on the current state.

The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and

FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other

and can have different frequencies. Switching the reference from one frequency to another does not require the

device reset to be applied. Table 20 on page 55 shows input frequency selection for the primary and secondary

reference respectively.

34

Zarlink Semiconductor Inc.

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