P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.26 KBI

The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can configure the port

via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is

used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to

define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, battery-powered systems that need to carefully manage power consumption

yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

7.27 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal

400 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by

a power-on reset. When the watchdog feature is disabled, it can be used as an interval

timer and may generate an interrupt. Figure 14 shows the watchdog timer in Watchdog

mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the

watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog

timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the

P89LPC9301/931A1 User manual for more details.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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