SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAF-C505C-2RM

8-bit Single-Chip Microcontroller

Infineon Technologies 

C505 / C505C

C505A / C505CA

Notes :

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,

or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the

0.9 VDD specification when the address lines are stabilizing.

3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port

pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits.

4) Not 100% tested, guaranteed by design characterization.

5) Only valid for C505A-4E and C505CA-4E.

6) Only valid for C505A-4E and C505CA-4E in programming mode.

7) IDD (active mode) is measured with:

XTAL1 driven with tR , tF = 5 ns, 50% duty cycle , VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;

EA = Port 0 = RESET =VDD ; all other pins are disconnected.

8) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;

RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode by

software;

9) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;

RESET = EA = VSS ; all other pins are disconnected; the microcontroller is put into slow-down mode by

software;

10) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;

RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode

with slow-down enabled by software;

11) IPD (power-down mode) is measured under following conditions:

Port 0 = EA = VDD ; RESET =VSS ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; VAREF = VDD ;

all other pins are disconnected.

12) The typical IDD values are periodically measured at TA = +25 °C but not 100% tested.

13) The maximum IDD values are measured under worst case conditions (TA = 0 °C or -40 °C and VDD = 5.5 V)

14) The values are valid for C505CA-4R, C505CA-2R, C505CA-L, C505A-4R, C505A-2R and C505A-L only.

Data Sheet

60

08.00

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