SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAF-C505C-2RM

8-bit Single-Chip Microcontroller

Infineon Technologies 

C505 / C505C

C505A / C505CA

Notes:

1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in

these cases will be 00H or FFH, respectively.

2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.

After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time tS, the time for determining the digital result. Values for the

conversion clock tADC depend on programming and can be taken from the table on the previous page.

4) TUE (max.) is tested at –40 ≤ TA ≤=125 °C ; VDD ≤ 5.5 V; VAREF ≤ VDD + 0.1 V and VSS= ≤ VAGND. It is

guaranteed by design characterization for all other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload

currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is

permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Data Sheet

65

08.00

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