PCA9541AD View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

PCA9541AD

2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors. 

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SDA_MST0(1)

slave address

command code register

data Control register

After the STOP condition

MASTER 1 is disconnected

from the downstream channel.

S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 1 0 1 0 0 A P

START condition

R/W

acknowledge

from slave

auto

increment

acknowledge

from slave

SCL_MST0

BUSINIT

BUSON

MYBUS

acknowledge

from slave

STOP

condition

INT1

SCL_SLAVE

SDA_SLAVE

INT0

if the interrupt is not masked

(BUSLOSTMSK = 0)

123456789

MASTER 1 has control of the bus

A

STOP command

if the interrupt is not masked

(BUSINITMSK = 0)

PCA9541 has control of the bus

MASTER 0

has control

of the bus

MASTER 0 must wait for the 'bus free time' value

(between STOP and START) defined in the I2C-bus specification

before sending commands to the downstream devices.

002aab609

(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus).

Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested)

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