ST7SCR
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 38. Typical Application with an External Clock Source
VOSC1H
VOSC1L
90%
10%
tr(OSC1)
tf(OSC1)
tw(OSC1H)
tw(OSC1L)
EXTERNAL
CLOCK SOURCE
OSC2
OSC1
Not connected internally
fOSC
IL
ST7XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
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