ST72521AR9TC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72521AR9TC
STMicroelectronics
ST72521AR9TC Datasheet PDF : 199 Pages
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ST72521M/R/AR
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
12.11.3 I2C - Inter IC Control Interface
Subject to general operating conditions for VDD,
fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I2C interface meets the
requirements of the Standard I2C communication
protocol described in the following table.
Symbol
Parameter
Standard mode I2C
Min 1)
Max 1)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
th(SDA) SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
tf(SDA)
tf(SCL)
SDA and SCL fall time
th(STA) START condition hold time
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
tw(STO:STA) STOP to START condition time (bus free)
Cb
Capacitive load for each bus line
4.7
4.0
250
0 3)
1000
300
4.0
4.7
4.0
4.7
400
Figure 109. Typical Application with I2C Bus and Timing Diagram 4)
Fast mode I2C
Min 1)
Max 1)
1.3
0.6
100
0 2)
900 3)
20+0.1Cb 300
20+0.1Cb 300
0.6
0.6
0.6
1.3
400
Unit
µs
ns
µs
ns
ms
pF
VDD
VDD
I2C BUS
4.7kΩ
SDA
START
4.7kΩ
100Ω
100Ω
SDAI
SCLI
ST72XXX
tsu(STA)
REPEATED START
tw(STO:STA) START
tf(SDA)
tr(SDA)
tsu(SDA) th(SDA)
STOP
SCK
th(STA) tw(SCKH) tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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