PIC12F609/615/617/12HV609/615
5.2.4.4
GP3/T1G(1, 2)/MCLR/VPP
Figure 5-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• a Timer1 gate (count enable), alternate pin(1, 2)
• as Master Clear Reset with weak pull-up
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
FIGURE 5-3:
BLOCK DIAGRAM OF GP3
MCLRE
VDD
Weak
Data Bus
RD
TRISIO
RD
GPIO
DQ
WR
CK Q
IOC
RD
IOC
Interrupt-on-
Change
Q S(1)
R
Write ‘0’ to GBIF
From other
GP<5:4, 2:0> pins
Reset
VSS
MCLRE
MCLRE
Input
Pin
VSS
QD
EN
Q1
QD
EN
RD GPIO
Note 1: Set has priority over Reset
2010 Microchip Technology Inc.
DS41302D-page 49