PIC12F609/615/617/12HV609/615
5.2.4.5
GP4/AN3(2)/CIN1-/T1G/
P1B(1, 2)/OSC2/CLKOUT
Figure 5-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC(2)
• Comparator inverting input
• a Timer1 gate (count enable)
• PWM output, alternate pin(1, 2)
• a crystal/resonator connection
• a clock output
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
FIGURE 5-4:
BLOCK DIAGRAM OF GP4
Data Bus
DQ
WR
WPU
CK Q
Analog(3)
Input Mode CLK(1)
Modes
VDD
Weak
RD
WPU
GPPU
Oscillator
Circuit
OSC1
CLKOUT
Enable
WR
GPIO
DQ
CK Q
WR
TRISIO
DQ
CK Q
RD
TRISIO
RD
GPIO
WR
IOC
DQ
CK Q
RD
IOC
FOSC/4 1
0
CLKOUT
Enable
INTOSC/
RC/EC(2)
CLKOUT
Enable
Analog
Input Mode
QD
EN
QD
Interrupt-on-
Change
Q S(4)
R
Write ‘0’ to GBIF
From other
GP<5, 3:0> pins
To T1G
To A/D Converter(5)
EN
RD GPIO
Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable.
2: With CLKOUT option.
3: Analog Input mode comes from ANSEL.
4: Set has priority over Reset.
5: PIC12F615/617/HV615 only.
VDD
I/O Pin
VSS
Q1
DS41302D-page 50
2010 Microchip Technology Inc.