PIC16C432-I View Datasheet(PDF) - Microchip Technology
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PIC16C432-I Datasheet PDF : 106 Pages
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PIC16C432
3.2.2.4 PIE1 Register
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 3-4:
PIE1 REGISTER (ADDRESS 8CH)
U-0
R/W-0
U-0
U-0
—
CMIE
—
—
bit7
bit 7
bit 6
bit 5-0
Unimplemented: Read as '0'
CMIE: Comparator Interrupt Flag bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
3.2.2.5 PIR1 Register
This register contains the individual flag bit for the com-
parator interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 3-5:
PIR1 REGISTER (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
—
CMIF
—
—
bit7
bit 7
bit 6
bit 5-0
Unimplemented: Read as '0'
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
U-0
U-0
U-0
U-0
—
—
—
—
bit0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
U-0
U-0
U-0
U-0
—
—
—
—
bit0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 13
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