PIC16C432-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C432-I Datasheet PDF : 106 Pages
| |||
PIC16C432
4.2 PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a High Impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins of RB<7:4> are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 4-5:
RBPU(1)
Data Bus
WR PORTB
WR TRISB(1)
BLOCK DIAGRAM OF
RB<7:4> PINS
VDD
Data Latch
DQ
P
Weak
Pull-up
I/O pin
CK
TRIS Latch
DQ
CK
TTL
Input
Buffer
ST
Buffer
Set RBIF
RD TRISB
RD PORTB
Latch
QD
EN
From other
RB<7:4> pins
QD
EN
RB<7:6> in Serial Programming mode
RD Port
Note 1: TRISB = 1 enables weak pull-up if RBPU = 0
(OPTION<7>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt-on-mismatch feature, together with
software configurable pull-ups on these four pins, allow
easy interface to a key pad and make it possible for
wake-up on key depression. (See AN552, “Implement-
ing Wake-up on Key Strokes”.)
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 4-6:
RBPU(1)
Data Bus
WR PORTB
WR TRISB(1)
BLOCK DIAGRAM OF
RB<3:0> PINS
VDD
Data Latch
DQ
P
Weak
Pull-up
I/O pin
CK
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRISB
RD PORTB
QD
EN
RB0/INT
ST
Buffer
RD Port
Note 1: TRISB = 1 enables weak pull-up if RBPU = 0
(OPTION<7>).
DS41140C-page 20
Preliminary
2000-2013 Microchip Technology Inc.
Share Link: 