PIC16LC62B-04E/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC62B-04E/SO Datasheet PDF : 120 Pages
| |||
PIC16C62B/72A
FIGURE 13-16: I2C BUS DATA TIMING
103
SCL
SDA
In
90
91
100
106
101
107
SDA
Out
Note:
109
109
Refer to Figure 13-4 for load conditions.
102
92
110
TABLE 13-12: I2C BUS DATA REQUIREMENTS
Param.
No.
100*
Sym
THIGH
Characteristic
Clock high time
100 kHz mode
400 kHz mode
101*
TLOW
Clock low time
SSP Module
100 kHz mode
400 kHz mode
102*
TR
SDA and SCL rise
time
SSP Module
100 kHz mode
400 kHz mode
103*
TF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
90*
91*
106*
107*
92*
109*
110*
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
Cb
START condition
setup time
100 kHz mode
400 kHz mode
START condition hold 100 kHz mode
time
400 kHz mode
Data input hold time 100 kHz mode
400 kHz mode
Data input setup time 100 kHz mode
400 kHz mode
STOP condition setup 100 kHz mode
time
400 kHz mode
Output valid from
clock
100 kHz mode
400 kHz mode
Bus free time
100 kHz mode
400 kHz mode
Bus capacitive loading
Min
Max Units Conditions
4.0
—
0.6
—
1.5TCY
—
4.7
—
1.3
—
1.5TCY
—
20 + 0.1Cb
—
1000
300
—
300
20 + 0.1Cb 300
4.7
—
0.6
—
4.0
—
0.6
—
0
—
0
0.9
250
—
100
—
4.7
—
0.6
—
—
3500
—
—
4.7
—
1.3
—
—
400
µs Device must operate at a min-
imum of 1.5 MHz
µs Device must operate at a min-
imum of 10 MHz
µs Device must operate at a min-
imum of 1.5 MHz
µs Device must operate at a min-
imum of 10 MHz
ns
ns Cb is specified to be from
10-400 pF
ns
ns Cb is specified to be from
10-400 pF
µs Only relevant for repeated
µs START condition
µs After this period the first clock
µs pulse is generated
ns
µs
ns Note 2
ns
µs
µs
ns Note 1
ns
µs Time the bus must be free
µs before a new transmission
can start
pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall-
ing edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT ≥
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
DS35008B-page 100
Preliminary
© 1998 Microchip Technology Inc.
Share Link: 