PIC16C62B/72A
FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
I/O Pins
Note: Refer to Figure 13-4 for load conditions.
30
34
31
34
FIGURE 13-8: BROWN-OUT RESET TIMING
VDD
BVDD
35
TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
31* Twdt Watchdog Timer Time-out Period 7
(No Prescaler)
—
— µs VDD = 5V, -40°C to +125°C
18
33 ms VDD = 5V, -40°C to +125°C
32
Tost Oscillator Start-up Timer Period — 1024 — — TOSC = OSC1 period
TOSC
33* Tpwrt Power-up Timer Period
28
72
132 ms VDD = 5V, -40°C to +125°C
34
TIOZ I/O Hi-impedance from MCLR
—
—
2.1 µs
Low or WDT reset
35
TBOR Brown-out Reset Pulse Width
100
—
— µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS35008B-page 92
Preliminary
© 1998 Microchip Technology Inc.