PIC16C745/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C745/SP

8-Bit CMOS Microcontrollers with USB

Microchip Technology 

PIC16C745/765

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The Special Function Registers can be classified into

two sets (core and peripheral). Those registers associ-

ated with the “core” functions are described in this sec-

tion, and those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name

Bank 0

00h

INDF(3)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Value on: Value on all

POR, other resets

BOR

(2)

0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

02h

PCL(3)

Program Counter's (PC) Least Significant Byte

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

03h

STATUS(3)

IRP(2)

RP1(2)

RP0

TO

PD

04h

FSR(3)

Indirect data memory address pointer

Z

DC

C

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

05h

PORTA

—

—

PORTA Data Latch when written: PORTA pins when read

--0x 0000 --0u 0000

06h

PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

07h

PORTC

RC7

RC6

—

—

—

RC2

RC1

RC0 xx-- -xxx uu-- -uuu

08h

PORTD(4) PORTD Data Latch when written: PORTD pins when read

xxxx xxxx uuuu uuuu

09h

PORTE(4)

—

—

—

—

—

RE2

RE1

RE0 ---- -xxx ---- -uuu

0Ah

PCLATH(1,3)

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

0Bh

INTCON(3)

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

0Ch

PIR1

PSPIF(4)

ADIF

RCIF

TXIF

USBIF

CCP1IF

TMR2IF TMR1IF 0000 0000 0000 0000

0Dh

PIR2

—

—

—

–

—

—

—

CCP2IF ---- ---0 ---- ---0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

—

Unimplemented

14h

—

Unimplemented

—

—

—

—

15h

CCPR1L Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

—

DC1B1

DC1B0

CCP1M3

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D 0000 -00x 0000 -00x

19h

TXREG USART Transmit Data Register

0000 0000 0000 0000

1Ah

RCREG USART Receive Data Register

0000 0000 0000 0000

1Bh

CCPR2L Capture/Compare/PWM Register2 (LSB)

xxxx xxxx uuuu uuuu

1Ch

CCPR2H Capture/Compare/PWM Register2 (MSB)

xxxx xxxx uuuu uuuu

1Dh

CCP2CON

—

—

DC2B1

DC2B1

CCP2M3

CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

1Eh

ADRES A/D Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0 ADCS1 ADCS0

CHS2

CHS1

CHS0

GO/DONE

—

ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: These registers can be addressed from either bank.

4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.

© 1999 Microchip Technology Inc.

Advanced Information

DS41124A-page 17

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