PIC16CE624T-04SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16CE624T-04SS

OTP 8-Bit CMOS MCU with EEPROM Data Memory

Microchip Technology 

10.5 Interrupts

The PIC16CE62X has 4 sources of interrupt:

• External interrupt RB0/INT

• TMR0 overflow interrupt

• PortB change interrupts (pins RB<7:4>)

• Comparator interrupt

The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which

re-enable RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag is contained in the special

register PIR1. The corresponding interrupt enable bit is

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine, the source(s) of

FIGURE 10-15: INTERRUPT LOGIC

CMIF

CMIE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

PEIE

GIE

PIC16CE62X

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RB0/INT

recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends on when the interrupt event occurs

(Figure 10-16). The latency is the same for one or two

cycle instructions. Once in the interrupt service routine

the source(s) of the interrupt can be determined by poll-

ing the interrupt flag bits. The interrupt flag bit(s) must

be cleared in software before re-enabling interrupts to

avoid multiple interrupt requests.

Note 1:

2:

Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

Wake-up

(If in SLEEP mode)

Interrupt

to CPU

© 1999 Microchip Technology Inc.

DS40182C-page 59

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