PIC16F1828T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1828T-I/SL

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

24.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1

is clocked by an external clock source.

PIC16(L)F1824/1828

24.1.6 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

APFCON1

CCPxCON

—

PxM1(1)

—

PxM0(1)

—

DCxB1

—

DCxB0

P1DSEL

CCPxM3

P1CSEL P2BSEL

CCPxM2 CCPxM1

CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)

CCPRxH Capture/Compare/PWM Register x High Byte (MSB)

CMxCON0 CxON

CxOUT

CxOE

CxPOL

—

CxSP

CxHYS

CMxCON1 CxINTP CxINTN CxPCH1 CxPCH0

—

—

CxNCH1

INLVLA

INLVLC

INTCON

—

—

INLVLC7(2) INLVLC6(2)

GIE

PEIE

INLVLA5

INLVLC5

TMR0IE

INLVLA4

INLVLC4

INTE

INLVLA3

INLVLC3

IOCIE

INLVLA2

INLVLC2

TMR0IF

INLVLA1

INLVLC1

INTF

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSP1IE

CCP1IE TMR2IE

PIE2

OSFIE

C2IE

C1IE

EEIE

BCL1IE

—

—

PIE3

PIR1

—

TMR1GIF

—

ADIF

CCP4IE

RCIF

CCP3IE

TXIF

TMR6IE

SSP1IF

—

CCP1IF

TMR4IE

TMR2IF

PIR2

OSFIF

C2IF

C1IF

EEIF

BCL1IF

—

—

PIR3

T1CON

—

—

CCP4IF CCP3IF

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

TMR6IF

T1OSCEN

—

T1SYNC

TMR4IF

—

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA

TRISC

—

—

TRISC7(2) TRISC6(2)

TRISA5

TRISC5

TRISA4

TRISC4

TRISA3

TRISC3

TRISA2

TRISC2

TRISA1

TRISC1

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Capture.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1828 only.

Bit 0

CCP2SEL

CCPxM0

CxSYNC

CxNCH0

INLVLA0

INLVLC0

IOCIF

TMR1IE

CCP2IE

—

TMR1IF

CCP2IF

—

TMR1ON

T1GSS0

TRISA0

TRISC0

Register

on Page

123

238

216*

216*

181

182

128

139

93

94

95

96

97

98

99

197

198

193*

193*

126

137

 2010 Microchip Technology Inc.

Preliminary

DS41419B-page 217

Share Link: