PIC16F1828T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1828T-I/SL

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

24.2.5 COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

PIC16(L)F1824/1828

24.2.6 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

APFCON1

CCPxCON

—

—

PxM<1:0>(1)

—

—

DCxB<1:0>

P1DSEL

P1CSEL P2BSEL CCP2SEL

CCPxM<3:0>

CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)

CCPRxH Capture/Compare/PWM Register x High Byte (MSB)

INLVLA

INLVLC

INTCON

—

—

INLVLC7(2) INLVLC6(2)

GIE

PEIE

INLVLA5

INLVLC5

TMR0IE

INLVLA4

INLVLC4

INTE

INLVLA3

INLVLC3

IOCIE

INLVLA2

INLVLC2

TMR0IF

INLVLA1

INLVLC1

INTF

INLVLA0

INLVLC0

IOCIF

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSP1IE

CCP1IE TMR2IE TMR1IE

PIE2

OSFIE

C2IE

C1IE

EEIE

BCL1IE

—

—

CCP2IE

PIE3

PIR1

—

TMR1GIF

—

ADIF

CCP4IE

RCIF

CCP3IE

TXIF

TMR6IE

SSP1IF

—

CCP1IF

TMR4IE

TMR2IF

—

TMR1IF

PIR2

OSFIF

C2IF

C1IF

EEIF

BCL1IF

—

—

CCP2IF

PIR3

T1CON

—

—

TMR1CS<1:0>

CCP4IF CCP3IF

T1CKPS<1:0>

TMR6IF

T1OSCEN

—

T1SYNC

TMR4IF

—

—

TMR1ON

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL

T1GSS<1:0>

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA

TRISC

—

—

TRISC7(2) TRISC6(2)

TRISA5

TRISC5

TRISA4

TRISC4

TRISA3

TRISC3

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1828 only.

Register

on Page

123

238

216*

216*

128

139

93

94

95

96

97

98

99

197

198

193*

193*

126

137

 2010 Microchip Technology Inc.

Preliminary

DS41419B-page 219

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