PIC16LF72-IP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF72-IP

28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter

Microchip Technology 

PIC16F72

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Details on

POR, BOR page:

Bank 2

100h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19

101h TMR0

Timer0 Module’s Register

xxxx xxxx 27

102h(1 PCL

Program Counter's (PC) Least Significant Byte

0000 0000 18

103h(1) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 12

104h(1) FSR

Indirect Data Memory Address Pointer

xxxx xxxx 19

105h

— Unimplemented

—

—

106h PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx 23

107h

— Unimplemented

—

—

108h

— Unimplemented

—

—

109h

— Unimplemented

—

—

10Ah(1,2) PCLATH

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 18

10Bh(1) INTCON

GIE

PEIE TMR0IE INTE

RBIE TMR0IF INTF

RBIF 0000 000x 14

10Ch PMDATL Data Register Low Byte

xxxx xxxx 35

10Dh PMADRL Address Register Low Byte

xxxx xxxx 35

10Eh PMDATH

—

— Data Register High Byte

--xx xxxx 35

10Fh PMADRH

—

—

— Address Register High Byte

---x xxxx 35

Bank 3

180h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19

181h OPTION RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 13

182h(1) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 18

183h(1) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 12

184h(1) FSR

Indirect Data Memory Address Pointer

xxxx xxxx 19

185h

— Unimplemented

—

—

186h TRISB

PORTB Data Direction Register

1111 1111 23

187h

— Unimplemented

—

—

188h

— Unimplemented

—

—

189h

— Unimplemented

—

—

18Ah(1,2) PCLATH

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 18

18Bh(1) INTCON

GIE

PEIE TMR0IE INTE

RBIE TMR0IF INTF

RBIF 0000 000x 14

18Ch PMCON1 — (3)

—

—

—

—

—

—

RD 1--- ---0 35

18Dh

— Unimplemented

—

—

18Eh

— Reserved, maintain clear

0000 0000

—

18Fh

— Reserved, maintain clear

0000 0000

—

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

This bit always reads as a ‘1’.

© 2007 Microchip Technology Inc.

DS39597C-page 11

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