PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology
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PIC16F1513T-I/SS Datasheet PDF : 360 Pages
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16.6 Hardware CVD Operation
Capacitive Voltage Divider is a charge averaging
capacitive sensing method. The hardware CVD module
will automate the process of charging, averaging
between the external sensor capacitance and the inter-
nal ADC sample and hold capacitor, and then initiating
the ADC conversions. The whole process can be
expanded into three stages: pre-charge, acquisition
and conversion. See Figure 16-10 for basic information
on the timing of three stages.
16.6.1 PRE-CHARGE TIMER
The pre-charge stage is an optional 1-127 instruction
cycle time delay used to put the external ADC channel
and the internal sample and hold capacitor (CHOLD)
into pre-conditioned states. The pre-charge stage of
conversion is enabled by writing a non-zero value to
the ADPRE<6:0> bits of the AADPRE register. This
stage is initiated when a conversion sequence is
started by either the GO/DONE bit or a Special Event
Trigger. When initiating an ADC conversion, if the
ADPRE bits are cleared, this stage is skipped.
During the pre-charge time, CHOLD is disconnected
from the outer portion of the sample path that leads to
the external capacitive sensor and is connected to
either VDD or VSS, depending on the value of the
ADIPPOL bit of the AADCON3 register. At the same
time, the port pin logic of the selected analog channel
is overridden to drive a digital high or low out in order to
pre-charge the outer portion of the ADC’s sample path,
which includes the external sensor. The output polarity
of this override is determined by the ADEPPOL bit of
the AADCON3 register.
When the ADOOEN bit of the AADCON3 register is set,
the ADOUT pin is overridden during pre-charge. See
Section 16.6.9 “Analog Bus Visibility” for more
information. This override functions the same as the
channel pin overrides, but the polarity is selected by the
ADIPPOL bit of the AADCON3 register. See
Figure 16-7.
16.6.2 ACQUISITION TIMER
The acquisition timer controls the time allowed to
acquire the signal to be sampled. The acquisition delay
time is from 1 to 127 instruction cycles and is used to
allow the voltage on the internal sample and hold
capacitor (CHOLD) to settle to a final value through
charge averaging. The acquisition time of conversion is
enabled by writing a non-zero value to the
ADACQ<6:0> bits of the AADACQ register. When the
acquisition time is enabled, the time starts immediately
following the pre-charge stage. If the ADPRE<6:0> bits
of the AADPRE register are set to zero, the acquisition
time is initiated by either setting the GO/DONE bit or a
Special Event Trigger.
PIC16(L)F1512/3
At the start of the acquisition stage, the port pin logic of
the selected analog channel is again overridden to turn
off the digital high/low output drivers so that they do not
affect the final result of charge averaging. Also, the
selected ADC channel is connected to CHOLD. This
allows charge averaging to proceed between the
pre-charged channel and the CHOLD capacitor. It is
noted that the port pin logic override that occurs during
acquisition related to the selected sample channel
does not occur on the ADOUT pin. See Section 16.6.9
“Analog Bus Visibility” for more information.
16.6.3 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
AADCON0 register must be set. Setting the GO/DONE
bit of the AADCON0 register or by the Special Event
Trigger inputs will start the Analog-to-Digital conversion.
Once a conversion begins, it proceeds until complete,
while the ADON bit is set. If the ADON bit is cleared, the
conversion is halted. The GO/DONE bit of the
AADCON0 register indicates that a conversion is
occurring, regardless of the starting trigger.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section Section 16.6.10 “Hard-
ware CVD Double Conversion Proce-
dure”.
16.6.4 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit of the AADCON0 register.
• Set the ADIF Interrupt Flag bit of the PIR1
register.
• Update the AADRESxH and AADRESxL registers
with new conversion results.
16.6.5 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
clear the GO/DONE bit. The AADRESxH and
AADRESxL registers will be updated with the partially
complete Analog-to-Digital conversion sample.
Incomplete bits will match the last bit converted.
The AADSTAT register can be used to track the status
of the hardware CVD module during a conversion.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
2012-2014 Microchip Technology Inc.
DS40001624C-page 139
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