PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1513T-I/SS

28-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

PIC16(L)F1512/3

16.6.6 DOUBLE SAMPLE CONVERSION

Double sampling can be enabled by setting the

ADDSEN bit of the AADCON3 register. When this bit is

set, two conversions are completed each time the

GO/DONE bit is set or a Special Event Trigger occurs.

The GO/DONE bit remains set for the duration of both

conversions and is used to signal the end of the

conversion.

Without setting the ADIPEN bit, the double conversion

will have identical charge/discharge on the internal and

external capacitor for these two conversions. Setting

the ADIPEN bit prior to a double conversion will allow

the user to perform a pseudo-differential CVD mea-

surement by subtracting the results from the double

conversion. This is highly recommended for noise

immunity purposes.

The result of the first conversion is written to the

AADRES0H and AADRES0L registers. The second

conversion starts two clock cycles after the first has

completed, while the GO/DONE bit remains set. When

the ADIPEN bit of AADCON3 is set, the value used by

the ADC for the ADEPPOL, ADIPPOL, and GRDPOL

bits are inverted. The value stored in those bit locations

is unchanged. All other control signals remain

unchanged from the first conversion. The result of the

second conversion is stored in the AADRES1H and

AADRES1L registers. See Figure 16-11 and

Figure 16-12 for more information.

16.6.7 GUARD RING OUTPUTS

The guard ring outputs consist of a pair of digital

outputs from the hardware CVD module. This function

is enabled by the GRDAOE and GRDBOE bits of the

AADGRD register. Polarity of the output is controlled by

the GRDPOL bit.

Once enabled and while ADON = 1, the guard ring

outputs are active at all times. The outputs are

initialized at the start of the pre-charge stage to match

the polarity of the GRDPOL bit. The guard output

signal, ADGRDA, changes polarity at the start of the

acquisition phase. The value stored by the GRDPOL bit

does not change. When in Double Sampling mode, the

ring output levels are inverted during the second

pre-charge and acquisition phases if ADDSEN = 1 and

ADIPEN = 1. For more information on the timing of the

guard ring output, refer to Figures 16-9, 16-11

and 16-12.

A typical guard ring circuit is displayed in Figure 16-8.

CGUARD represents the capacitance of the guard ring

trace placed on a PCB board. The user selects values

for RA and RB that will create a voltage profile on

CGUARD, which will match the selected channel during

acquisition.

The purpose of the guard ring is to generate a signal in

phase with the CVD sensing signal to minimize the

effects of the parasitic capacitance on sensing

electrodes. It also can be used as a mutual drive for

mutual capacitive sensing. For more information about

active guard and mutual drive, see Application Note

AN1478, “mTouchTM Sensing Solution Acquisition

Methods Capacitive Voltage Divider” (DS01478).

FIGURE 16-8:

GUARD RING CIRCUIT

ADGRDA

RA

ADGRDB

RB

CGUARD

DS40001624C-page 140

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