PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology
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PIC18LC658-I/CL Datasheet PDF : 366 Pages
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PIC18CXX8
6.1 Operation
Example 6-1 shows the sequence to perform an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
MOVFF
MULWF
ARG1, WREG ;
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
MOVFF
MULWF
BTFSC
SUBWF
MOVFF
BTFSC
SUBWF
ARG1, WREG
ARG2
ARG2, SB
PRODH, F
ARG2, WREG
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 6-3 shows the sequence to perform a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 6-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 =
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
MOVFF
MOVFF
;
MOVFF
MULWF
MOVFF
MOVFF
;
MOVFF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
;
MOVFF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
ARG1L, WREG
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, WREG
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, WREG
ARG2H
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
ARG1H, WREG
ARG2L
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
DS30475A-page 72
Advanced Information
2000 Microchip Technology Inc.
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