PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology
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PIC18LC658-I/CL Datasheet PDF : 366 Pages
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PIC18CXX8
7.1.2 PIR REGISTERS
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON register).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
REGISTER 7-4: RCON REGISTER
R/W-0
R/W-0
U-0
IPEN
LWRT
—
bit 7
7.1.3 PIE REGISTERS
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Enable registers (PIE1, PIE2, PIE3). When IPEN is
clear, the PEIE bit must be set to enable any of these
peripheral interrupts.
7.1.4 IPR REGISTERS
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts
(Register 7-7). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt Prior-
ity registers (IPR1, IPR2, IPR3). The operation of the
priority bits requires that the Interrupt Priority Enable bit
(IPEN) be set.
7.1.5 RCON REGISTER
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable
For details of bit operation see Register 4-3
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
For details of bit operation see Register 4-3
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-3
bit 2 PD: Power-down Detection Flag bit
For details of bit operation see Register 4-3
bit 1 POR: Power-on Reset Status bit
For details of bit operation see Register 4-3
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-3
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS30475A-page 80
Advanced Information
2000 Microchip Technology Inc.
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