PIC18F2331/2431/4331/4431
FIGURE 26-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
SDO
SDI
80
MSb
bit 6 - - - - - -1
MSb In
74
73
75, 76
bit 6 - - - -1
LSb
77
LSb In
TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS to SCK or SCK Input
TssL2scL
TCY
—
71
TscH
SCK Input High Time
Continuous 1.25 TCY + 30 —
71A
Single byte
40
—
72
TscL
SCK Input Low Time
Continuous 1.25 TCY + 30 —
72A
Single byte
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
—
75
TdoR
SDO Data Output Rise Time
PIC18FXX31
—
25
PIC18LFXX31
—
45
76
TdoF
SDO Data Output Fall Time
—
25
77
TssH2doZ SS to SDO Output High-Impedance
10
50
80
TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXX31
—
50
TscL2doV
PIC18LFXX31
—
100
83
TscH2ssH, SS after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
2010 Microchip Technology Inc.
DS39616D-page 355