PIC18F44J10T-I/ML(2009) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F44J10T-I/ML
(Rev.:2009)

28/40/44-Pin High-Performance, RISC Microcontrollers

Microchip Technology 

PIC18F45J10 FAMILY

FIGURE 24-18: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TX/CK

pin

RX/DT

pin

121

121

120

122

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param

No.

Symbol

Characteristic

Min

Max

120 TCKH2DTV SYNC XMIT (MASTER and SLAVE)

Clock High to Data Out Valid

—

40

121 TCKRF Clock Out Rise Time and Fall Time (Master mode)

—

20

122 TDTRF Data Out Rise Time and Fall Time

—

20

Units Conditions

ns

ns

ns

FIGURE 24-19:

TX/CK

pin

RX/DT

pin

EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

125

126

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min Max

125 TDTV2CKL SYNC RCV (MASTER and SLAVE)

Data Hold before CK ↓ (DT hold time)

126 TCKL2DTL Data Hold after CK ↓ (DT hold time)

10

—

15

—

Units

ns

ns

Conditions

© 2009 Microchip Technology Inc.

DS39682E-page 333

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