PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE
(MASTER MODES ONLY) (ACCESS F6Fh)(1)
R/W-0
—
bit 7
R/W-0
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Parallel Master Port Address High Byte<13:8>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-0
Unimplemented: Maintain as ‘0’
CS1: Chip Select bit
If PMCON<7:6> = 10:
1 = Chip select is active
0 = Chip select is inactive
If PMCON<7:6> = 11 or 00:
Bit functions as ADDR<14>.
Parallel Master Port Address: High Byte<13:8> bits
Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
REGISTER 11-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE
(MASTER MODES ONLY) (ACCESS F6Eh)(1)
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Parallel Master Port Address Low Byte<7:0>
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Parallel Master Port Address: Low Byte<7:0> bits
Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.
2011 Microchip Technology Inc.
DS39931D-page 177
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